1. Field of the Invention
The present invention generally relates to frequency synthesizers and to modulator circuits used in frequency synthesizers, and more particularly, the present invention relates to sigma-delta modulated fractional-N frequency synthesizers.
This is a counterpart of, and claims priority to, Korean Application No. P2000-0059408, filed Oct. 10, 2000, the entirety of which is incorporated herein by reference.
2. Background of the Invention
There is increasing demand for a variety of real-time multimedia wireless services, including real-time video, internet access, and so on. These necessitate high-speed connections with the wireless or mobile communication terminals. Reflective of this trend towards higher transmission speeds, the standard CDMA-2000 1X (2.5G) is configured such that 144-kbps data service is available at existing CDMA/PCS bands.
Wireless communications terminals commonly utilize radio-frequency (RF) frequency synthesizers to achieve programmable channel selection. To operate, for example, in the high-speed environment dictated by the CDMA-2000 1X standard, the RF frequency synthesizer should preferably exhibit a settling time of less than 500 μs, a frequency resolution of 10 KHz, and a phase noise of less than 135 dBc/Hz at about 1 MHz offset frequency. As discussed below, conventional RF frequency synthesizers are not ideally suited to meet these preferred characteristics associated with the CDMA-2000 1X standard.
FIGS. 7-10 illustrate a sigma-delta controlled fractional-N frequency synthesizer as is described in Norman M. Filiol et al., “An Agile ISM Band Frequency Synthesizer with Built-In GMSK Data Modulation,” IEEE JSSC, vol. 33, pp. 998-1008, July 1998, the entirety of which is incorporated herein by reference. Sigma-delta modulation of fractional-N frequency synthesizers is also described in [1] Philip S. Gaskell et al., U.S. Pat. No. 5,079,521, issued Jan. 7, 1992; [2] Thomas A. D. Riley et al., U.S. Pat. No. 5,781,044, issued Jul. 14, 1998; [3] Thomas A. D. Riley, U.S. Pat. No. 4,965,531, [4] Brian Miller et al., “A Multiple Modulator Fractional Divider,” IEEE Trans. Instrument and Measurement, vol. 40, no. 3, pp. 578-583, June 1991; [5] Terrance P. Kenny et al., “Design and Realization of a Digital Delta Sigma Modulator for Fractional-n Frequency Synthesis,” IEEE Trans. Vehicular Tech., vol. 48, no. 2, pp. 510-521, March 1999; and [6] Woogeun Rhee et al., “A 1.1 GHz CMOS Fractional-N Frequency Synthesizer with a 3rd-Order Delta Sigma Modulator,” ISSCC 2000, pp. 198-199, 2000. The entirety of each of these documents is incorporated herein by reference.
Referring to FIG. 7, a target frequency ftarget is fed to the input of the sigma-delta modulator 702 in the form of a digital word. A modulated output bit stream b(t) is applied to and controls the operation of the dual-modulus divider 704 contained in the feedback of a phase-locked-loop (PLL). The PLL includes the divider 704, a phase detector 706, a loop filter 708, and a voltage-controlled-oscillator (VCO) 710.
The average value of b(t) corresponds to the division ratio required to output the desired output frequency fout. The dual-modulus divider 704 outputs a phase control signal fd, which is the N or N+1 (depending on b(t)) divided output frequency fout. The phase control signal ftarget is applied the phase detector 706, which compares the phase control signal fd with an input reference signal fref.
The signal provided at the output of phase detector 706 is proportional to the phase difference between the reference signal fref and the phase control signal fd. This signal is filtered by the (low pass) loop filter 708, resulting in a normaly d.c. voltage, and applied to control the VCO 701 which generates the output frequency fout.
FIG. 8 is a functional block diagram of the dual-modulus divider 704 shown in FIG. 7. The input b(t) to the divider is a single-bit control which allows 0 or 2 rad of phase (0 or 1 period of the VCO 710) to be subtracted every reference cycle from the input signal fout. The subtraction is followed by a fixed divide by N as shown, resulting in the phase control signal fd.
Sigma-delta modulators achieve high resolution from a single-bit quantizer through the use of noise-shaping and oversampling techniques. Higher order modulators have fewer limit cycle tones, and higher in-band signal-to-noise ratios. When designing higher order sigma-delta modulators, stability becomes a concern due to high-order feedback around the loop. An alternative to this approach is to use a MASH architecture.
A MASH architecture sigma-delta modulator is shown in FIG. 9. In this case, the modulator is a cascade of first-order sigma-delta modulators. The quantization error of each stage is fed forward to the next stage, whose output bitstream is a sigma-delta quantized estimate of the error from the previous stage. The outputs are then combined in a noise-shaping block which cancels the noise from the first n−1 stages, producing a multi-bit output which has nth-order noise shaping given asN(z)=(1−z−1)n. Here, n denotes the order or number of stages. FIG. 10 illustrates the frequency spectrum of a fourth-order (n=4) MASH modulator.
An advantage of this modulator architecture resides in its stability since no nth-order feedback is present and the first-order stages are stable. A primary disadvantage resides in its multi-bit output, making multi-modulus divider necessary in the feedback of the synthesizer PLL.
Moreover, the performance of the previously proposed fractional-N frequency synthesizers is generally unsatisfactory with respect to out-of-band phase noise at around 1 MHz offset or in obtaining an accurate frequency resolution of 10 kHz. Further, the synthesizer exhibit large spurs of −40 dBc under particular operating conditions, resulting in roadblocks to their actual use. It is inferred that this is because the nonlinearity of a PFD or a multi-modulus divider occurring in an actual PLL does not comport with the high linearity of the PLL which is required in using a multi-bit modulator and a MASH-type modulator. Furthermore, the previous synthesizers suffer large spurs at a particular operating condition that results from nonlinearity in the phase-frequency detector and the multi-modulus divider when multi-bit modulators and MASH-type modulators are used as a fractional division controller in PLL. For at least these reasons, conventional RF frequency synthesizers are not ideally suited to meet these preferred characteristics associated with the CDMA-2000 1X standard.